Synopsys High Performance Computing
Ken Brock — Synopsys
The physical implementation of processors in the 1980s and the 1990s was centered on the custom circuit design and layout of the heart of the processor: the speed-critical circuits that are dependent on the physical layout of the chips's main datapath. Datapath layout structures, popularized by the 1980 Mead and Conway methodology, were used to minimize these physical effects. A second generation of tools and methodologies developed by Silicon Compilers, Seattle Silicon Technology and Compass Design Automation addressed creating libraries for high-performance cores through semi-custom datapath structures, with the goal of managing these physical effects with datapath cells and standard cells to provide a flexible solution for multiple types of processors. Synthesis changed all of this, and by the end of the 1990s fully synthesizable processor cores became available.
With some of today's synthesizable cores targeting clock speeds over 2 GHz, it is critical to understand both the science and the art of using high-performance logic libraries to obtain the best performance, power, and area (PPA).
This article discusses the best technology and techniques for hardening CPU cores. These are fundamental principles that apply to CPU cores that are targeted to achieving the optimal PPA from the silicon process. You will learn proven best practices and solutions that can be immediately applied to your core optimization project to achieve best results.
A Word about Critical Paths
To achieve optimal processor performance you must reduce the delay in the critical paths of your design. These critical paths can be in your register-to-register paths (logic) or the memory access paths to/from the L1/L2 caches. All paths must meet their constraints in order to achieve timing closure.
Figure 1. The left image shows the most critical register-to-register path and the right image shows the memory paths to and from the L1 cache of a GHz CPU.
To keep memory timing out of the critical path, you can:
- Use high-performance memory compilers to generate the optimal configurations of memory instances required for your design over the set of processor memory configurations.
- Start with a good initial floorplan to minimize the physical distance between the memory I/O pins and the critical registers within the processor logic. The ability to change this floorplan is critical as your design progresses and you start applying engineering tradeoffs to achieve your goals.
A good floorplan based on the number of cores and the rest of your system-on-chip (SoC) interconnectivity requirements can minimize the physical distance in the top level of the design and reduce timing bottlenecks.
You will need four things to harden your high-performance core:
- A high-performance EDA tool flow
- High-performance logic libraries with power optimization kits
- High-performance memory compilers in the required configurations
- High-density logic libraries and memory compilers for the rest of the SoC that may operate at lower frequencies than the high-performance core
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